| Intel Corporation. Santa Clara, CA |
| Senior Director, High-Performance Computing |
Jan'19 – Present |
- Leading a 600+ strong engineering organization with a 600M+ annual budget, responsible for EDA Computing
services to over 125 chip design projects.
- In-depth collaboration with Engineering Design teams, working on cutting-edge silicon products, to optimize the EDA workloads and IT offerings for optimal design execution.
- Collaborated with networking team to optimize the network thruputs with a data center as well as for data transfer to remote data centers. Collaborated with InfoSec team to ensure the HPC services are secure and compliant with the latest security standards.
- Initiated many employee engagement and development programs such as innovation, tech-talks, and
upskilling that
resulted in an engaged and committed team.
- Developed a customer-first mindset across the entire team. Emphasized the importance of data
transparency and power of
intuitive self-services to improve productivity
- Developed confident and empowered leaders; encouraged risk-taking while ensuring well-thought-out
risk-reward trade-offs
- Geo-spread team managed large compute and NFS server farms across many data centers, ensuring
world-class
uptime and operational costs.
- Supported execution of 200M+/week EDA batch jobs; employed deep analytics to optimize batch jobs to
improve design flows to run 70% faster while reducing compute demand by 50%.
|
| Director, Design Automation and IT |
Apr'17 – Dec’18 |
- Directed automation activities for server SoCs that generated multi-billion dollars in sales and
fueled the company's revenues and growth.
- Design Automation responsibility for all XEON class projects. Co-optimizing EDA tools and flows with
computing infrastructure.
- Supporting 3200+ design engineers working on 100+ IP and SoC projects.
- Managing 200+PB of raw NFS storage. Executive Sponsor for vendor relationship, negotiated resolution
to current issues and
plans for future deliverables.
- Transformed the mindset of 80+ engineers to develop a customer-centric mindset that internalizes the
various workloads and their unique requirements.
- Motivating the team for greater customer interaction to influence design automation. Identified
optimizations in SoC
design data storage resulting in a 57% reduction in the number of files stored and improving replication
performance by over 5X.
- Implemented AGILE method of work transformation to active predictable and high-quality results.
|
| Engineering Manager, Design Automation |
May'11 – Apr’17 |
- Managing a geo dispersed team supporting server CPU design teams around the globe. Responsible for
enabling a large portfolio of projects critical to company’s future success in areas such as Data
Center, Networking, Artificial Intelligence, and Autonomous Driving.
- Leading efforts to drive consistency in the tool/flow/methodology used by nearly 100 design teams.
Established efficient engagement models to provide tool support and drive methodology across large a
number of teams.
- Directed the development of web-based dashboards to manage concurrent development of several SoCs
and IPs. The dashboards provide detailed information about IP readiness quality status, model
performance, compute utilization, and user usage data among many other details required to productively
manage the work of >3000 design engineers.
- Regular engagement with high-level managers at EDA vendors to drive Intel requirements and manage
the delivery of enhancement and bug fixes. Participate in technical meetings to define solutions.
- Leading several workgroups chartered to improve tool/flow performance or designer productivity.
Designed methods for disciplined root cause and data mining that enable significant improvements in
tool/flow runtime or significant reduction of load on compute farm or network fileservers. These
changes directly improved design environment productivity and stability.
- Built a strong team by growing the team with >20 engineers, hired in a span of 8 months. Marketed
the
openings in my team at hiring events and hired several candidates from these events.
- Mentored several individual contributors to successfully transition to management roles as project
leads or first-line managers. Held regular coaching sessions with new managers to analyze challenges and
help them come up with solutions.
- Managed the compute farm and fileservers used by >3000 engineers. Working with the computing group in
defining the compute requirements and set up to provide a highly efficient environment to a large team
of design engineers. Negotiating service level agreements and methods to measure and monitor compute
environment performance. Technical debug with senior engineers to root cause and fix computing
bottlenecks. Help identify tool/flow issues that were causing compute bottlenecks.
|
| Design Manager |
Jan'02 – Apr’11 |
- Led a team of 20+ design engineers working on backend activities from physical
synthesis to tape-out for server chipsets. Successfully delivered 5 tape-outs.
- Defined, implemented, and supported RTL-2-GDS flow including routing, placement, extraction, and manual
layout cleanup.
- Collaborated with Digital Design Engineering, IO designers, and Tapeout services to ensure high
quality, on-schedule tape-outs.
Negotiated with leading CAD tool vendors on bug fixes, priorities, and release schedules.
- Managed the memory compiler project for server CPUs. Managed the automation development of
register files (RFs) generation which was used to generate 100+ tape-out quality RFs.
- Lead the synthesis design flow and methodology definition and development. Architected the “last
mile” flows for layout
clean-up to pull-in schedule by several weeks and reduced layout cleanup effort by several man-years.
- Lead the post-silicon clean-up of electrical and performance issues. Created and managed test patterns
generation flows for bin-splitting. Implemented a fully automated flow that improved the pattern generation time from
several weeks to a few hours.
|
| CAD Engineer and Project Leader |
Sep'95 - Jan’02 |
- Project Lead for the next generation of the Data Path layout planner tool. Managed all aspects of tool
development requirement gathering, code reviews, and customer validation with microprocessor projects.
- Defined the architecture for the tool, very closely involved in the implementation of the core data
model and the GUI. Implemented user interface components and usage flows.
- Worked with design teams located at various Intel sites and presented tool education sessions at
internal conferences.
- Developed algorithms and state-of-the-art CAD tools for Data Path Layout Automation for Intel's next
generation of microprocessors. Engaged with design engineering customers across many geo-spread
locations for training
and support.
|
Berkeley Technical leadership Program, Berkeley, CA.
Ph.D. in Computer Engineering, Syracuse University, Syracuse, NY.
Thesis: “Congestion Driven Global Routing and Cross Point Assignment”
M.Sc. in Computer Engineering, Syracuse University, Syracuse, NY.
B.Sc. (Honors) in Electrical Engineering. University of Khartoum, Khartoum.